1. Field of the Invention
The present invention generally relates to a voltage monitor circuit.
2. Background of the Invention
A voltage monitor circuit is included in an electrical device such as a cellular telephone or a personal digital assistant (PDA) for monitoring the voltage level of a battery used to operate the device. The voltage monitor circuit ensures that the electrical device is operative only when a desired minimum level of battery voltage is present. When the battery voltage falls below the desired minimum voltage level, the voltage monitor circuit signals the electrical device to shut down. The voltage monitor circuit inhibits further operation of the electrical device until the battery voltage is restored.
FIG. 1 illustrates the typical behavior of the battery voltage over time for a battery being operated in an electrical device. In FIG. 1, it is assumed that a fully charged battery is inserted into the electrical device at time T0. When a fully charged battery is inserted, the battery voltage as seen by the electrical device increases rapidly (but not immediately due to the charging of capacitors) to a maximum voltage value as shown by curve 12a. A voltage monitor circuit associated with the electrical device detects when the battery voltage increases to a value greater than a predefined low threshold voltage, V.sub.T (Low), and signals the electrical device to begin operation. The battery voltage decreases as the battery charge is consumed (curve 12b). When the battery voltage falls below the low threshold voltage, VT(Low), at time T2 in FIG. 1, the voltage monitor circuit detects the low voltage condition and signals the electrical device to shut down its circuits. Ideally, the electrical device should not operate again until the battery charge is fully restored or restored to a sufficiently high level. However, as described below, the electrical device is often caused to operate before the battery is restored sufficiently because the battery voltage exhibits the well-known phenomenon called "bounce back" as illustrated by curve 12c in FIG. 1.
Because the battery voltage is load dependent, when the electrical device shuts down its circuits, the load on the battery is reduced and the battery voltage will recover to a value above the low threshold voltage, V.sub.T (Low). The electrical device sees what is apparently a valid operating voltage on the battery and turns on its circuit again. However, because only minimal battery charge actually remains, the battery voltage will almost immediately fall below the low threshold level V.sub.T (Low) again and the device will have to shut off its circuits almost as soon as it turns them on. Therefore, it is undesirable to operate the device under what is called the "bounce back" voltage.
To prevent device operation under the "bounce back" voltage, conventional voltage monitor circuits are typically designed with hysteresis. Two threshold voltages are used to control the proper operation of an electrical device: a high threshold voltage, V.sub.T (High), and a low threshold voltage, V.sub.T (Low). Referring again to FIG. 1, when a voltage monitor circuit employs hysteresis, an electrical device will not turn on unless the battery voltage has reached V.sub.T (High) which is at time T1 in FIG. 1. After time T1, the electrical device will operate until the battery voltage falls below V.sub.T (Low) which occurs at time T2 in FIG. 1. After time T2, even though the battery voltage recovers to above V.sub.T (Low), the voltage monitor circuit will prevent the electrical device from turning on because the battery voltage has not increased above V.sub.T (High). In this manner, the voltage monitor circuit precludes operation under the "bounce back" voltage.
The amount of hysteresis, i.e., the voltage values of V.sub.T (Low) and V.sub.T (High), of a voltage monitor circuit is established based on the type of battery and the load placed on the battery by the electrical device or electrical system. The threshold voltages V.sub.T (Low) and V.sub.T (High) are optimized individually for each electrical device or electrical system in which a voltage monitor circuit operates.
FIG. 2 is a circuit schematic of a conventional voltage monitor circuit 20 with adjustable hysteresis. Voltage monitor circuit 20 includes a resistor network including serially connected resistors 24, 26, and 28, a first comparator 38, a second comparator 40, and a latch 48. The resistor network is connected across the battery voltage (V.sub.BAT) to be monitored (node 22) and a ground potential (node 30). Resistors 24, 26, and 28 operate as a voltage divider to scale battery voltage V.sub.BAT down to provide two reference voltage levels for monitoring the battery voltage. A high battery voltage monitor level (V.sub.High) is provided at node 34 between resistors 26 and 28. V.sub.High is a scaled voltage for monitoring a high level of the battery voltage. A low battery voltage monitor level (V.sub.High) is provided at node 32 between resistors 24 and 26. V.sub.Low is a scaled voltage for monitoring a low level of the battery voltage.
First comparator 38 compares voltage V.sub.Low to a reference voltage V.sub.Ref (node 36). Because V.sub.Low is connected to the inverting input terminal of first comparator 38, first comparator 38 provides a low to high transition on output lead 42 when voltage V.sub.Low decreases from a value above V.sub.Ref to a value below V.sub.Ref. Second comparator 40 compares voltage V.sub.High also to reference voltage V.sub.Ref (node 36). Because V.sub.High is connected to the non-inverting terminal of second comparator 40, second comparator 40 provides a low to high transition on output lead 44 when voltage V.sub.High increases from a value below V.sub.Ref to a value above V.sub.Ref. Output lead 42 of first comparator 38 is connected to the reset terminal of latch 48. Output lead 44 of second comparator 40 is connected to the set terminal of latch 48. Latch 48 provides an output signal Power Good on output lead 50. Signal Power Good indicates the status of the battery voltage to the electrical device in which voltage monitor circuit 20 operates. When signal Power Good is at a high logic level, the battery charge is within the desirable operative range. When signal Power Good is at a low logic level, the battery charge is below the desirable operative range.
In operation, second comparator 40 monitors the positive-going transition of battery voltage V.sub.BAT, that is, the increase in battery voltage illustrated by curve 12a in FIG. 1. At time T0, signal Power Good is low and voltage monitor circuit 20 is monitoring voltage V.sub.High. Between time T0 and T1, the battery voltage is below V.sub.T (High), thus, voltage V.sub.High is less than V.sub.Ref and the output of comparator 40 is at a low logic level. Latch 48 is not set and signal Power Good remains at a low logic level. At time T1, the battery voltage reaches V.sub.T (High), voltage V.sub.High is now greater than V.sub.Ref and output lead 44 of second comparator 40 transitions to a high logic level, setting latch 48. Signal Power Good transitions to a high logic level as a result. Voltage monitor circuit 20 then monitors voltage V.sub.Low. Between time T1 and T2, the battery voltage is above V.sub.T (Low). Thus, V.sub.Low is greater than V.sub.Ref and output lead 42 is at a low logic level. Signal Power Good remains set to a high logic level. At time T2, when the battery voltage drops below V.sub.T (Low), first comparator 38 provides a high logic level output on lead 42 causing latch 48 to reset. Signal Power Good thus transitions to a low logic level. Signal Power Good will remain at a low logic level, indicating inoperative battery charge, until second comparator 40 detects that the battery voltage has increased above V.sub.T (High) again. In this manner, voltage monitor circuit 20 ensures that no chattering occurs on signal Power Good and the electrical device will not be operated under the "bounce back" voltage.
The conventional voltage monitor circuit such as circuit 20 in FIG. 2 has several disadvantages. First, in voltage monitor circuit 20, latch 48 effects the hysteresis for the monitor circuit as a whole and prevents chattering of signal Power Good on output lead 50. However, each of comparators 38 and 40 must have its own hysteresis to prevent chattering of the comparator output (i.e. output leads 42 and 44). The hysteresis required for each of the comparators degrades the offset of the comparator and compromises the accuracy of voltage monitor circuit 20.
Secondly, the use of two comparators complicates system design. The two-comparator circuit requires a system designer to manage two separate and unrelated comparator offset values, further degrading the performance of the monitor circuit. If trimming is needed to improve the comparator offset, then at least two separate trims must be performed.
Lastly, voltage monitor circuit 20, including two comparators and a latch, not only consumes more power, but also results in a larger device size. When voltage monitor circuit 20 is implemented as an integrated circuit, the two-comparator and latch design consumes valuable die area and increases the cost of fabrication. Furthermore, power consumption is increased by internal transitions occurring in comparators 38 and 40 that do not affect output signal Power Good.
Therefore, it is desirable to provide a voltage monitor circuit with adjust hysteresis using only a single comparator and avoiding the disadvantages mentioned above.